The present invention relates to semiconductor devices and methods of fabrication and operation. More specifically, the invention relates to flash memory devices having a 3-dimensional arrangement of memory cell arrays and methods of fabricating same and operating same.
The demand for higher performance at lower cost continues to drive the integration density of contemporary semiconductor devices. In this regard, semiconductor devices having 3-dimensionally arranged (or vertically stacked) transistors have been proposed. In many 3-dimensional flash memory devices, a well region associated with a bottom (or lower) memory cell array and a well region associated with a top (or upper) memory cell array are connected to each other. As a result, the bottom and top memory cell arrays cannot be independently controlled during an erase or program operation.